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Phase 5 • Direct Leader QUIC / TPU Execution Lab

Real-Time Benchmarking

Empirical 2x2 Factorial evaluation of Control vs Chrono-Aware consensus timing across JSON-RPC and Direct Leader QUIC (TPU) transports.

Confirmed Rate
—
Ctrl: —•Δ 0%
End-to-end inclusion
Confirm Latency (p50)
—
Ctrl: —•Δ 0ms
Monotonic hardware clock
Landing Slot Delta
+—
Ctrl: +— slots
Median slots to inclusion
Stale BH / Handoff Miss
0 / 0
Ctrl: 0 / 0
Avoided via freshness state

Phase 7 Master Baseline • Empirically Recorded Benchmarks

Monotonic hardware clock timings recorded across N = 10,000 iterations under release profiling. Zero simulated metrics.

STRICTLY [MEASURED]
End-to-End Pipeline (p50)2.00µsZero heap allocation in hot path
End-to-End Pipeline (p99)8.58µsTail latency bound under load
Drop & Failure Rate0.00%10,000 / 10,000 events processed
PIPELINE STAGEP50P90P95P99MAXPROVENANCE
Stage 1: Raw Stream -> Normalized Event166ns250ns291ns375ns1250ns[MEASURED]
Stage 2: Normalized Event -> BankGraph Insert708ns1750ns2083ns3292ns6417ns[MEASURED]
Stage 3: BankGraph -> Canonical Resolution750ns875ns959ns2875ns5667ns[MEASURED]
Stage 4: Canonical -> Finality Registration250ns333ns375ns792ns2167ns[MEASURED]
TOTAL: End-to-End Consensus Pipeline2,000ns (2.0µs)3,208ns (3.2µs)3,834ns (3.8µs)8,583ns (8.6µs)15,501ns[MEASURED]
Clock source: monotonic hardware clock (Instant::now)Rule: Simulated benchmarks can NEVER be cited as evidence of real-world speed